In each new generation of semiconductor processing, a variety of changes are observed, such as, increasing processing and tooling costs, increasing design, verification and testing costs, and increasing development and deployment time. The rate of these changes is greater than the rate of change of the input/output (I/O) requirements of the devices. In addition, the improved logic and memory area reduction that each new process generation provides does not scale equally with circuits that include I/O and non-logic structures, such as, for example, analog, phase locked loop (PLL), voltage regulator, and electro static discharge (ESD) structures, because these circuits use thick oxide transistors. Many semiconductor devices become bound by the I/O of a die, and the logic and memory density in each new process is sometimes limited by the number of I/Os.